1. Field of the Invention
The present invention relates to an integrated circuit having memory cells. The integrated circuit according to the present invention is used for a memory device having a redundant circuit portion for replacing failed circuits.
2. Description of the Related Art
In general, an integrated circuit device for a semiconductor memory is provided with "redundant-bit" type memory cells in addition to the usually used memory cells. These are used to replace failed memory cells or even to replace an entire bit line containing failed memory cells, in the latter case by a redundant bit line containing redundant memory cells. This increases the yield of the products in the manufacture of integrated circuits.
In such an integrated circuit, read-only memories (ROM's) are provided for storing the addresses of the failed memory cells. When an input address signal coincides with the address of a failed memory cell stored in the ROM's, the circuit is switched to access a redundant memory cell instead of the failed memory cell. Accordingly, quick and correct detection of the written state of the ROM's is important.
However, 2.sup.n+1 cycles are usually required for detecting the written state of the ROM's. Hence, a very long time is required for testing an integrated circuit.
Also, when several fuses are used for each bit in the ROM's, it is impossible to determine the blow-out state of each of the fuses, although the output state of the ROM's can be determined. This is undesirable and causes problems in an integrated circuit device for a semiconductor memory.